Multilayer wiring structures are widely used in printed boards and ceramic substrates having laminated ceramic green sheets. When the wiring structures are manufactured, techniques for connecting lower metal wiring elements and upper metal wiring elements, being separated by interlayer insulation layers, to each other through via holes are used. Especially, in recent years and continuing, techniques for connecting lower metal wiring elements and upper metal wiring elements to each other through small via holes are attracting interest due to an increasing demand for higher density mounting on printed wiring boards and ceramic substrates along with a trend toward more highly integrated and higher speed LSIs.
The manufacturing process of the printed boards and ceramic substrates uses screen printing as a method of filling via holes. If the diameter of a via hole is several hundreds μm, the via hole can be easily filled with a conductive paste by screen printing.
However, if the diameter of the via hole is as small as about 100 μm, air in the via hole is not completely removed by the conductive paste, so that unwanted air bubbles and voids remain in the via hole filled with the conductive paste. As a result, the contact resistance of the via hole is increased, which lowers output signal and frequency properties. The increase of contact resistance lowers long-term reliability of the printed boards and ceramic substrates.
Patent Document 1 entitled “MANUFACTURING METHOD OF PRINTED WIRING BOARD” discloses a method of filling small via holes.
According to the method disclosed in Patent Document 1, with reference to FIG. 16, a via hole 50 is filled with a conductive paste 15 with use of a screen mask 17 having an ejection hole 44 with a diameter greater than the diameter of the via hole 50. Then, the conductive paste 15 is heated and cured while a substrate 51 is vibrated at 1-100 Hz. During curing of the conductive paste 15, air bubbles and voids in the via hole 50 are pushed out by the vibration and the vacated space is filled with the conductive paste 15. Therefore, neither air hole nor air gap remains in the via holes 50.
However, when the via hole 50 has a smaller diameter, a conductive paste 15 having higher viscosity is used. As the viscosity increases, removal of the air bubbles and gaps by vibration becomes more difficult and incomplete. In one embodiment illustrated in Patent Document 1, the method is used for filling the via hole 50 having a diameter of 100 μm with the conductive paste (Ag paste) 15 having a viscosity of 1000-3000 Pa·s. It seems that this method cannot be used for filling a via hole having a diameter smaller than 100 μm. Another problem with this method is that a special heating oven is required for generating vibration of 1-100 Hz.
Another method of filling small via holes is disclosed in Patent Document 2 entitled “SCREEN PRINTING METHOD AND METHOD FOR MANUFACTURING LAMINATED CERAMIC ELECTRONIC PART”.
According to the method disclosed in Patent Document 2, with reference to FIG. 17, two squeegees having different attack angles are arranged in a moving direction. A process of printing upper metal electrodes and a process of filling via holes are simultaneously performed while two squeegees move toward same direction on the surface of the object to be printed. Since the attack angle of the squeegee arranged upstream in the moving direction is relatively large, the upper electrodes can be formed without blur. On the other hand, since the attack angle of the squeegee arranged downstream in the moving direction is relatively small, the via holes can be efficiently filled.
However, the squeegee used for filling the via holes is the one arranged downstream in the moving direction. Using a squeegee having a small attack angle for filling via holes is well known in the art. Therefore, it seems to be difficult to fill via holes smaller than conventional via holes by using the method of Patent Document 2. The main advantage of the method of Patent Document 2 is that via holes having about the same size as the conventional via holes can be filled while printing the upper electrodes without blur.
Patent Document 3 discloses a method of connecting upper metal wiring elements and lower metal wiring elements through small via holes. According to Patent Document 3, with reference to FIGS. 18A-18E, a columnar conductor 46 of conductive paste is formed on a lower metal wiring element 45. Then, the lower metal wiring element 45 and the columnar conductor 46 are covered with an insulation layer 47. The surface of the insulation layer 47 is polished by mechanical polishing until a head of the columnar conductor 46 is exposed. An upper metal wiring element 49 is then formed on the polished insulation layer 47, so that the lower metal wiring element 45 and the upper metal wiring element 49 are connected to each other. The method of Patent Document 3 does not inherently have the problem related to air bubbles and voids remaining in via holes because the columnar conductor 46 is used in place of a via hole filled with a conductive paste.
Electric circuits formed on printed wiring boards and ceramic wiring boards include various capacitors, inductors, resistors, and LSIs. A technique for embedding the capacitors into the boards is attracting attention because of demand for higher signal speed and higher mounting density.
According to a well-know method, an internal capacitor is formed by applying a dielectric paste and then sandwiching the dielectric paste with upper and lower electrodes.
However, the capacitor formed using this method occupies a relatively large area and prevents high density mounting on the board even if the size of via holes is reduced. For this reason, smaller internal capacitors are needed.
A method of forming small internal capacitors is disclosed in Patent Document 4.
According to the method of Patent Document 4, a hole for capacitor paste and a hole for a plating post are formed on a lower metal wiring element. Then, the hole for the capacitor paste is filled with the capacitor paste by screen printing, and then the plating post is formed in the other hole by plating. After that, photoresist is removed, and the capacitor paste and the plating post are covered with an interlayer of insulating resin. The surface of the insulation resin interlayer is polished with a buff or the like by mechanical polishing so as to expose heads of the capacitor paste and the plating post. An upper metal wiring element is then formed on the capacitor paste and the plating post. Thus, a multilayer wiring structure having an internal capacitor and the upper and lower metal wiring elements connected through the via holes is formed.
The method disclosed in Patent Document 1 utilizes the method disclosed in Patent Document 3, and can form small internal capacitors with use of a capacitor paste containing a filler of a suitable relative dielectric constant.
A common problem for the methods disclosed in Patent Documents 3 and 4 is that dust is generated during the polishing process for exposing the head of the columnar conductor 46 (the capacitor paste and the plating metal), and the dust might cause contact failure if deposited on an interface between the columnar conductor 46 (the capacitor paste and the plating metal) and the upper metal wiring element 49. A cleaning process is therefore added after the mechanical polishing process, making the manufacturing process more complex. Moreover, polishing machines and cleaning machines increase the cost of manufacturing equipment. In addition, a larger production space is required because the polishing machines and cleaning machines are needed to be isolated from other work spaces in order to prevent the dust from scattering. As for the method disclosed in Patent Document 4, the reliability of the internal capacitor is lowered if air bubbles and voids are present between the interlayer insulating resin and the capacitor paste.
As can be seen from the above description, filling small via holes is a big challenge in manufacturing printed boards and ceramic substrates having multilayer wiring structures.
Flat panel displays including, e.g., liquid crystal display devices, EL devices, and electrophosphorescent devices use multilayer wiring structures having relatively loose DR. Because higher definition, faster response, and lower costs are important for the flat panel displays, techniques for manufacturing active matrix drive circuits at low cost are needed.
The active matrix drive circuits have been manufactured using LSI production techniques such as photolithography and dry etching. However, DRs of the metal wiring width and via holes are about 10-100 μm, and the LSI production techniques are the over specifications. For this reason, printing techniques, especially wiring processes using screen printing, are attracting interest as lower cost production methods.
Screen printing has been already put into practical use in producing printed wiring boards and ceramic substrates. The minimum line width of metal wires achieved with use of a conductive paste is 30-50 μm at the mass production level and 10-30 μm at the research level. Metal wiring of the active matrix drive circuits are expected to be realized by applying such a screen printing technique to production of the active matrix drive circuits.
However, the active matrix drive circuits also have multilayer wiring structures, and there are almost no techniques for printing a via hole with a diameter as small as about 50-100 μm in interlayer insulation films. Therefore, laser drilling and photolithography and dry etching are mainly used in research and development. Moreover, techniques for filling holes of 50-100 μm with conductive paste are not yet established as in the case of the printed wiring boards and the ceramic substrates.
Screen printing uses a screen mask with an emulsion pattern for printing via holes. The emulsion pattern formed on the screen mask corresponding to via holes is an isolated pattern. For example, there is about only one node in an emulsion pattern having a diameter of 50 μm formed on a screen mask of 380-590 meshes for high definition printing. Therefore, the emulsion pattern more easily comes off from the screen mask compared to conventional screen masks. Since the emulsion pattern may possibly come off during production of the screen mask, it is very difficult to produce the screen mask having no defects. Even if a defect-free screen can be produced, an emulsion pattern formed thereon easily comes off during printing. Thus, the life of the screen mask is much shorter compared to conventional screen masks.
As can be seen, manufacturing a defective-free and long-life screen mask for forming via holes as well as completely filling small via holes with a conductive paste are big technical problems in forming active matrix drive circuits by screen printing in the production process of the flat panel displays.
In recent years, TFTs (organic TFTs) using organic semiconductors have been attracting attention as switching elements of active matrix drive circuits of flat panel displays.
Although crystalline organic semiconductors such as pentacene have high mobility and are therefore promising in terms of high speed drive, the crystalline organic semiconductors are disadvantageous in that production of large-size and uniform semiconductors is difficult because of the use of vacuum deposition as well as in that they are easily oxidized because of relatively low ionization potential.
On the other hand, polythiophene, polyphenylene vinylene, and polyfluorene, etc., are suitable materials for the flat panel displays because these materials are soluble in an organic solvent and therefore deposition using spin coat methods or inkjet methods, which can produce large-size and uniform semiconductors, are applicable.
Especially, triaryl amine polymer is more readily soluble than other materials, and therefore easily adjusted when used in solution for spin coat methods and inkjet methods. Moreover, the triaryl amine polymer is not easily oxidized due to relatively high ionization potential, and therefore has high long-term reliability. For these reasons, development of the triaryl amine polymer has been intensively studied.
However, because the above organic semiconductor materials soluble in an organic solvent are easily solved in a developer and a remover used during photolithography, it is difficult to process such organic semiconductors by using photolithography. In addition, after the organic semiconductors are covered with an interlayer insulation film, the developer and the remover might penetrate through the interface between the organic semiconductors and the interlayer insulation film and dissolve the organic semiconductors during the process of forming via holes and pixel electrodes. It is therefore preferable to avoid photolithography.
Thus, a technique for printing a via hole having a diameter of about 50-100 μm in the interlayer insulation film covering the organic semiconductors is especially needed for producing the flat panel displays comprising the organic TFTs, but almost no such technique exists currently as described above.
Generally, the organic semiconductor materials that are soluble in an organic solution have low glass transition temperatures and therefore are easily damaged by heat and plasma. Also, if via holes are formed in the interlayer insulation films by laser drilling and dry etching, the Ion/Ioff and mobility of the organic TFTs are lowered. Therefore, the technique for printing a via hole in the interlayer insulation films is strongly desired in view of switching performance of the organic TFTs as well.
It is preferable to fill a via hole having a diameter of 50-100 μm with a conductive material by printing without using photolithography in the process of forming pixel electrodes as well, but such a technique is not yet established as described above.
Using the flat panel displays as electronic paper has been attracting attention. In many flat panel displays that maintain indications even if power is off, capacitors for accumulating charges are provided in parallel with TFTs. Therefore, there is a strong demand for a method of embedding small capacitors into active matrix drive circuits. Since the electronic paper requires lightness, slimness, rigidity, memory properties, film substrates having a thickness of 0.1-0.2 mm are used substrates of the active matrix drive circuits of the flat panel displays in place of glass substrates. Also, display elements having memory properties are used in the flat panel displays.
The film substrates shrink significantly in heating process. Therefore, if the TFTs are formed by dry etching, the substrates shrink when heated during the process of baking resists and forming films and cause misalignment between upper and lower layers. Especially, if a large-size substrate is used as in the active matrix drive circuits, a big alignment error between the upper and lower layers is caused near the substrate. In the worst case, a via hole is brought out of contact with a TFT and a pixel electrode and fails to connect the TFT to the pixel electrode, resulting in a defective bit. Therefore, the flat panel displays (electronic paper) using the film substrates cannot have as much pixels as the flat panel displays using the glass substrates.
Patent Document 5 entitled “FORMATION OF INTERLAYER INSULATING FILM IN MULTILAYER INTERCONNECTION” relates to contact holes of the same magnification sensors. According to a method disclosed in Patent Document 5, an interlayer insulation film is formed by screen printing, and a contact hole is formed therein. Then, an upper electrode is formed to fill the contact hole. Since the interlayer insulation film is formed by screen printing, the interlayer insulation film having a large flat surface can be formed. Accordingly, occurrence of disconnection of the upper electrode formed on the interlayer insulation film can be prevented.
<Patent Document 1> Japanese Patent Laid-Open Publication No. 2001-274547
<Patent Document 2> Japanese Patent Laid-Open Publication No. 2003-48303
<Patent Document 3> Japanese Patent Laid-Open Publication No. 11-87925
<Patent Document 4> Japanese Patent Laid-Open Publication No. 9-11624
<Patent Document 5> Japanese Patent Laid-Open Publication No. 61-13646
As described above, the problem with the related art methods of manufacturing multilayer wiring structures is that, if the via hole has a diameter as small as about 100 μm, air in the via hole is not completely removed by the conductive paste, so that unwanted air bubbles and voids remain in the filled via hole. Another problem is that, when the via hole has a smaller diameter, the conductive paste having higher viscosity is used, resulting in making the removal of the air bubbles and voids by vibration more difficult and incomplete. Using a squeegee having a small attack angle for filling via holes is well known in the art, and it seems to be difficult to fill via holes smaller than conventional via holes using the method of Patent Document 2. According to some methods, a cleaning process is added after the mechanical polishing process, which makes the manufacturing process more complex. Moreover, polishing machines and cleaning machines increase the cost of manufacturing equipment. In addition, a larger production space is required because the polishing machines and cleaning machines are needed to be isolated from other work spaces in order to prevent the dust from scattering.
It is preferable for the method of manufacturing a flat display comprising organic TFTs to avoid photolithography after covering the organic semiconductors with interlayer insulation film, because the organic semiconductor materials are easily dissolved in the developer and the remover used during photolithography.
Therefore, with reference to FIGS. 19A and 19B1-19B2, a technique for printing a via hole having a diameter of about 50-100 μm in an interlayer insulation film 23 covering a semiconductor and a technique for filling a via hole with a conductive material by a printing method are important. However, almost no such techniques are available now, and it is difficult to produce flat panel displays having high image quality. For now, only experimental production of displays using some materials is being carried out.
The organic semiconductor materials have low glass transition temperatures and therefore are easily damaged by heat and plasma. Also, if via holes are formed in the interlayer insulation films by laser drilling and dry etching, switching performance of the organic TFTs is lowered.